1. Field of the Invention
The present invention relates to a test circuit for a semiconductor IC circuit such as a semiconductor memory device, and specifically to a test circuit for a non-volatile semiconductor memory device such as, for example, a flash memory device.
2. Description of the Related Art
Next generation flash memory devices are required to operate at a lower voltage, to consume less power, and to be produced at lower cost. In order to be able to operate at a lower voltage, a flash memory device generally includes a boost circuit or charge pump circuit for boosting a voltage supplied from an external device. While the flash memory device is in a standby state, the charge pump circuit inactivates the boost operation so that the boosted output voltage is allowed to be decreased to a lowest possible level without causing any problems in operation. While the flash memory device is in an active state, the charge pump circuit outputs the voltage at the boosted level. Flash memory devices are required to be tested before shipping while in a wafer and after packaging to assure that the flash memory devices operate normally when switched from the standby state to the active state.
One of the tests performed at this stage is measurement of a potential of an output node of the charge pump circuit. A conventional test circuit 400 for measuring a potential at an output node VPX of a charge pump circuit 29 will be described with reference to FIG. 4.
The test circuit 400 of a flash memory device includes a low frequency oscillator (hereinafter, referred to as the xe2x80x9cLFOxe2x80x9d) 28 for causing the charge pump circuit 29 to operate in an intermittent manner, word line driving circuits 27 for driving word lines WL1 through WLn, row decoders 26, and an address transition detection (ATD) circuit 30 for detecting an address transition. The charge pump circuit 29, the row decoders 26, and the word line driving circuits 27 each have a conventional structure and will not be described in detail.
The test circuit 400 operates in the following manner.
The charge pump circuit 29 boosts a voltage Vcc supplied by an external power supply to a higher boosted voltage VH (shown in FIG. 5). Also shown in FIG. 5 is VL, which refers to a minimum operable voltage required to guarantee a normal operation of a flash memory device including the charge pump circuit 29. The boosted voltage VH is used as a feed voltage for each row decoder 26 and each word line driving circuit 27. The boosted voltage VH appears at the output node VPX of the charge pump circuit 29. The row decoders 26 respectively output the boosted voltage VH or a voltage Vss (GND) to the word line driving circuits 27, as outputs X1 through Xn, in accordance with signals A1 through An sent from a pre-decoder (not shown).
Each of the word line driving circuits 27 is an inverter buffer including a p-channel MOS transistor and an n-channel MOS transistor. The word line driving circuits 27 invert the signals at the output sections X1 through Xn. Each of memory cells in a memory array (not shown), gates of which are connected to corresponding word lines WL1 through WLn, are switched to a selected state or an unselected state in accordance with the inverted output.
In order to maintain the power consumption at a low level while the flash memory device is in a standby state, the charge pump circuit 29 is controlled to operate in an intermittent manner by a signal LFOP (low frequency oscillator""s pulse) from the LFO 28. When the flash memory device is switched into an active state, for example, a read state, the charge pump circuit 29 is controlled by a signal output from the address transition detection circuit 30, which has detected an address transition.
The operation of the test circuit 400 while the flash memory is in a standby state will be described.
FIG. 5 is a diagram illustrating exemplary changes in output voltages from the LFO 28 and the charge pump circuit 29 while the flash memory device is in a standby state. The changes will be described with reference to FIGS. 4 and 5.
The LFO 28 includes a ring oscillator and the output voltage LFOP is switched between a high level Vcc and a low level Vss with a certain period T. The charge pump circuit 29 is activated to perform a boost operation while, for example, the output signal LFOP is at the high level Vcc, to boost the voltage at the output node VPX to a predetermined boosted level VH. While the LFOP is at the low level Vss, the boost operation is not performed by the charge pump circuit 29. Thus, the charge pump circuit 29 itself consumes substantially no power; i.e., the charge pump circuit 29 is in a rest state. In this state, the output node VPX of the charge pump circuit 29 is at a high impedance and therefore is in a floating state. The node VPX is connected to a number of circuits (e.g., row decoders 26 and word line driving circuits 27) and accordingly has a large parasitic capacitance. The potential of the output node VPX is maintained at a certain degree by the accumulation of charges in the parasitic capacitance, but is gradually decreased by, for example, discharge caused by a leak current such as an off-leak current of the p-channel MOS transistor in the word line driving circuits 27. However, when the period T passes, the output signal LFOP of the LFO 28 returns to the high level Vcc. Therefore, the charge pump circuit 29 is activated and starts the boost operation. The voltage at the output node VPX is increased to the boosted level VH while the signal LFOP is at the high level Vcc.
Next, the operation of the test circuit 400 when the flash memory device is switched from a standby state to an active state will be described.
FIG. 6 is a diagram illustrating exemplary changes in the output voltages from the LFO 28 and the charge pump circuit 29 and an exemplary change in a chip enable signal /CE which are seen when the flash memory device is switched from a standby state to an active state. Such changes will be described also with reference to FIG. 4. When the flash memory device is in a standby state, the chip enable signal /CE is at the high level Vcc; and when the flash memory device is switched to an active state, the chip enable signal /CE becomes the low level Vss.
When the flash memory device is switched from a standby state to an active state, i.e., a read state, the charge pump circuit 29 detects that the flash memory device is in the read state by a signal output from the address transition detection circuit 30 which has detected an address transition, not by the output signal LFOP from the LFO 28. The charge pump circuit 29 is maintained in a constantly active state, and the voltage at the output node VPX is kept at the boosted level VH. However, there is a delay-time period TD until the charge pump circuit 29 is activated to output the predetermined boosted voltage VH after the chip enable signal /CE becomes the low level Vss.
Accordingly, immediately after the chip enable signal /CE becomes low, the word lines WL are driven while the voltage at the output node VPX is still low by the discharge. In order to normally access the word lines WL at a satisfactorily high access speed in this state, the potential at the output node VPX needs to be maintained at a sufficiently high above the minimum operable voltage VL even when the flash memory device is in a standby state. However, increasing the oscillation frequency of the LFO 28 in order to maintain the potential at the output node VPX sufficiently higher than the minimum operable voltage VL will result in increasing the power consumption while the flash memory device is in a standby state. In order to avoid this, the oscillation frequency of the LFO 28 and the like are set so that the potential at the output node VPX is kept slightly higher than the minimum operable voltage VL.
When, for example, the off-leak current of the p-channel MOS transistor in the word line driving circuits 27 is excessively large or the oscillation frequency of the LFO 28 is not sufficiently high due to the device-to-device dispersion in the device characteristics, the voltage at the output node VPX can undesirably become lower than the minimum operable voltage VL.
This can cause malfunction or extend the access time. In order to avoid such undesirable effects, the potential at the output node VPX needs to be measured while the flash memory device is in a wafer or after packaging. Flash memory devices having a voltage lower than the voltage VL in a standby state especially need to be eliminated before being put into the market.
While the charge pump circuit 29 is in the constantly active state, i.e., a read state, the potential at the output node VPX can easily be measured through a potential measurement pad 25 by closing a switch 24 (FIG. 4). The switch 24 is controlled by a control signal sent from a test control circuit (not shown) which operates in a test mode. The test control circuit is included in the flash memory device.
The charge pump circuit 29 operates in an intermittent manner while the flash memory device is in a standby state, and the node VPX is in a floating state while the charge pump circuit 29 is in a rest state. Since the charges accumulated in the output node VPX are discharged through a measuring device (not shown) through the potential measurement pad 25 when the switch 24 is closed, accurate measurement of the potential cannot be obtained in a similar manner as used when the charge pump circuit 29 is in the constantly active state.
This results in flash memory devices having a voltage lower than the minimum operable voltage VL in a standby state not being eliminated while the flash memory devices are in wafers. As a result, defective flash memory devices are sent to the packaging stage, which causes extra cost. There is also an undesirable possibility that the defective flash memory devices are not found in the test after packaging and are subsequently put to the market.
Measures taken to avoid the above-mentioned problems cause other problems as follows. Adopting higher-grade specifications results in a lower production yield and raises costs. Setting, for example, the oscillation frequency of the LFO 28 at a higher level at the designing stage results in an increase in the power consumption.
According to one aspect of the invention, a test circuit for a semiconductor IC device for measuring a potential at an output node of a boost circuit included in the semiconductor IC device includes a switch having an end connected to the output node: a potential measurement terminal; and an n-channel MOS transistor including a gate connected to another end of the switch, a source connected to a reference voltage supply, and a drain connected to the potential measurement terminal.
In one embodiment of the invention, the potential measurement terminal is an internal pad of the semiconductor IC device.
In one embodiment of the invention, the potential measurement terminal is an external pad of the semiconductor IC device.
In one embodiment of the invention, the potential measurement terminal is one of a signal input terminal, a signal output terminal and a signal input and output terminal while the semiconductor IC device is in a normal operation mode. The test circuit further includes another switch provided between the potential measurement terminal and the drain of the n-channel MOS transistor.
According to another aspect of the invention, a test circuit for a semiconductor IC device for measuring a potential at an output node of a boost circuit included in the semiconductor IC device includes a switch having an end connected to the output node; a first potential measurement terminal and a second potential measurement terminal; an n-channel MOS transistor including a gate connected to another end of the switch, a source connected to a reference voltage supply, and a drain connected to the first potential measurement terminal; and another switch having an end connected to the gate of the n-channel MOS transistor and another end connected to the second potential measurement terminal.
In one embodiment of the invention, the first and second potential measurement terminals are internal pads of the semiconductor IC device.
In one embodiment of the invention, the first and second potential measurement terminals are external pads of the semiconductor IC device.
In one embodiment of the invention, the first potential measurement terminal is one of a signal input terminal, a signal output terminal and a signal input and output terminal while the semiconductor IC device is in a normal operation mode. The second potential measurement terminal is one of a signal input terminal, a signal output terminal and a signal input and output terminal while the semiconductor IC device is in a normal operation mode. The test circuit further includes still another switch provided between the first potential measurement terminal and the drain of the n-channel MOS transistor.
Thus, the invention described herein makes possible the advantage of providing a test circuit for a semiconductor IC device realizing accurate potential measurement.
This and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.